1. Technical Field
The present invention relates generally to integrated circuits, and more particularly, to a method and apparatus for enhancing the soft error rate immunity of dynamic logic circuits.
2. Related Art
A dynamic complementary metal oxide semiconductor (CMOS) logic gate includes a logic structure having a precharge or output node, hereafter referred to as a “dynamic node,” that is precharged to the supply voltage using a clocked p-channel device (e.g., a precharge PFET). The dynamic node is conditionally discharged (evaluated) to external ground (GND) through a clocked n-channel device (e.g., an evaluate NFET) by a set of devices forming the logic structure.
The clocked p-channel device has its gate coupled to an input precharge signal (PC). The dynamic node is “precharged” through a p-channel device to the supply voltage when PC is low. When PC goes high, the dynamic node is conditionally discharged (evaluated) through the clocked n-channel device to GND. The dynamic node is discharged if the input signals to the devices forming the logic structure (e.g., an AND or OR logic structure) have configured a conducting path to GND, otherwise the dynamic node stays charged high.
The amount of charge on a dynamic node of a dynamic logic gate is sensitive to soft errors caused by natural radiation sources, such as alpha particles and cosmic rays. For example, the charge on a dynamic node may be reduced below the charge threshold (Qcrit) necessary to alter the state of the node from high (logic 1) to low (logic 0) as charge is “knocked off” the dynamic node as a result of the circuit's interaction with an alpha particle. This is especially problematic for dynamic nodes having a low Qcrit.
Qcrit will continue to decrease as feature size and power requirements are scaled downward as a result of advances in CMOS process technology. As a result, soft error rates (SER) are likely to increase. Accordingly, there is a need in the art for a method and apparatus for enhancing the soft error rate immunity of dynamic logic circuits.
One technique that has been used to increase the SER robustness of a dynamic logic circuit involves increasing the capacitance on the dynamic node. This increases Qcrit because the charge Q on the dynamic node is proportional to capacitance (i.e., Q=C*V). Unfortunately, by increasing the capacitance, the speed of the dynamic logic circuit is often reduced. Accordingly, there is a need in the art for an apparatus for enhancing the SER immunity of dynamic logic circuits by increasing the capacitance on the dynamic node, which is capable of being selectively deactivated to increase the performance (e.g., speed) of the dynamic logic circuit.